# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple aarch64 -run-pass=legalizer -verify-machineinstrs %s -o - | FileCheck %s

...
---
name:            s32_legal
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $w0
    ; CHECK-LABEL: name: s32_legal
    ; CHECK: %copy:_(s32) = COPY $w0
    ; CHECK: %bitreverse:_(s32) = G_BITREVERSE %copy
    ; CHECK: $w0 = COPY %bitreverse(s32)
    ; CHECK: RET_ReallyLR implicit $w0
    %copy:_(s32) = COPY $w0
    %bitreverse:_(s32) = G_BITREVERSE %copy
    $w0 = COPY %bitreverse
    RET_ReallyLR implicit $w0
...
---
name:            s64_legal
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: s64_legal
    ; CHECK: %copy:_(s64) = COPY $x0
    ; CHECK: %bitreverse:_(s64) = G_BITREVERSE %copy
    ; CHECK: $x0 = COPY %bitreverse(s64)
    ; CHECK: RET_ReallyLR implicit $x0
    %copy:_(s64) = COPY $x0
    %bitreverse:_(s64) = G_BITREVERSE %copy
    $x0 = COPY %bitreverse
    RET_ReallyLR implicit $x0
...
---
name:            v8s8_legal
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $x0
    ; CHECK-LABEL: name: v8s8_legal
    ; CHECK: %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    ; CHECK: %bitreverse:_(<8 x s8>) = G_BITREVERSE %vec
    ; CHECK: $x0 = COPY %bitreverse(<8 x s8>)
    ; CHECK: RET_ReallyLR implicit $x0
    %vec:_(<8 x s8>) = G_IMPLICIT_DEF
    %bitreverse:_(<8 x s8>) = G_BITREVERSE %vec
    $x0 = COPY %bitreverse
    RET_ReallyLR implicit $x0
...
---
name:            v16s8_legal
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $q0
    ; CHECK-LABEL: name: v16s8_legal
    ; CHECK: %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    ; CHECK: %bitreverse:_(<16 x s8>) = G_BITREVERSE %vec
    ; CHECK: $q0 = COPY %bitreverse(<16 x s8>)
    ; CHECK: RET_ReallyLR implicit $q0
    %vec:_(<16 x s8>) = G_IMPLICIT_DEF
    %bitreverse:_(<16 x s8>) = G_BITREVERSE %vec
    $q0 = COPY %bitreverse
    RET_ReallyLR implicit $q0
...
